Assignment A function generator produces waveforms at user-selected frequencies. You will design and implement an FPGA based function generator that supports frequencies from 10Hz to 10kHz

ELEE1156 Hardware Systems and Control Coursework Assignment

1. Introduction

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Through lab exercises and lectures, you have gained experience in implementing VHDL designs using various techniques. You will now apply these skills to design and build a function generator.

This project will allow you to demonstrate your abilities in VHDL design hardware interfacing, and simulation.

2. Assignment

A function generator produces waveforms at user-selected frequencies. You will design and implement an FPGA based function generator that supports frequencies from 10Hz to 10kHz and offers the following waveform options:

• PWM waveform with adjustable duty cycle
• Sine waveform

Design the function generator using VHDL and implement it on the DE1-SoC development board, using the board`s buttons, switches, LEDs, and seven-segment displays to create a user-friendly interface. 

2.1 Simulation

Simulation of the system can be done using ModelSim (or Questa). Relevant simulation should include verification of waveform generation.

2.2 Hardware implementation

Implement the system in hardware and use the DE1-SoC board`s LEDs and/or seven segment displays to visually indicate the output. FPGA output can be connected to the Texas Instruments TLC7524CN DAC to generate an analogue signal for devices like oscilloscopes or speakers.

2.3 Report

You should produce a report (maximum 1500 words, excluding appendices), in pdf format, that gives a comprehensive account of the design process including the hardware setup, VHDL code development, testing and evaluation.

A recommended structure for the report includes the following main headings, with subheadings added as appropriate:

• Introduction
• Design methodology
• VHDL development
• Testing and Results
• Evaluation and reflection
• Conclusion

VHDL code must be appropriately commented and developed using an appropriate design technique (block diagrams, state machine diagrams etc. as appropriate). 

Full listings of the VHDL files that you developed should be included in an appendix, although code excerpts may also be used in the main body of the report to illustrate a particular point.  Listings of VHDL code for any external IP blocks that are used do not have to be included in the report.

Relevant references should be included where appropriate.

3. Assessment

The report must be uploaded to Moodle, in pdf format, using the upload link provided in the ‘Coursework Briefing, Guidance and Submission’.  The report must be uploaded by the due date, which can be seen by clicking the upload link.

This assignment is a summative assessment and contributes 40% to your final module grade.

You can view the assessment rubric by clicking the assignment upload link on the module`s Moodle page

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